We’re seeking a Senior Design Verification Engineer to join our organization. This person will be a critical part of setting up the DV strategy and test benches for a brand new ASIC.
This person needs to be both strategic and tactical in their approach, operate independently and have the knowledge and confidence to set up the systems.
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Develop a design verification methodology suitable for a variety of implementations ranging from FPGAs to ASICs.
Work closely and collaboratively with RTL and analog designers, as well as algorithm developers and architects.
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Logic simulation skills including testbench design, stimulus generation, coverage, equivalence-checking, and debug.
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Mixed-signal (analog + digital) simulation.
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Proficiency in UVM and a hardware description language such as System Verilog
If interested in hearing more, please apply to the position and we can set up a time to discuss.
