Marvell Demonstrates Industry’s First 3nm Data Infrastructure Silicon

The blue eye diagram, PCIe Gen 6 SerDes (@ 64Gb/s), represents high-performance signals transmitted by Marvell’s 3nm SerDes optimized for PCIe Gen 6 / CXL 3.0. This is an industry-first. The vertical height, size, and relative symmetry of the eyes indicate the mitigation of noise and bit errors.Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions, has demonstrated high-speed, ultra-high bandwidth silicon interconnects produced on Taiwan Semiconductor Manufacturing Company’s (TSMC) 3-nanometer (3nm) process. Marvell’s industry-first silicon building blocks in this node include 112G XSR SerDes (serializer/de-serializer), Long Reach SerDes, PCIe Gen 6 / CXL 3.0 SerDes, and a 240 Tbps parallel die-to-die interconnect.

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